1. Field of the Invention
The present invention relates to a control circuit suitable for a PLL (Phase Locked Loop) frequency synthesizer apparatus, and particularly to a control circuit for varying frequency-divided values (N values) every reference cycles, which is suitable for use in a fractional N (Fractional Number)-type PLL frequency synthesizer apparatus.
2. Description of the Related Art
A fractional N-type PLL frequency synthesizer apparatus features that since it can set a division ratio for fractional values or numbers, a reference frequency can be set to twice by a natural number as large as a frequency step desired to be changed and correspondingly the time constant of a loop filter can be reduced, thereby making it possible to provide high-speed lockup and low noise (high C/N). The fractional N-type PLL frequency synthesizer apparatus is provided with a control circuit (hereinafter called "fractional N-type control circuit") for changing N values every reference cycles.
A related art of the fractional N-type control circuit will be shown in FIG. 1. In the same drawing, 2-bit frequency-divided value (N value) data (A, B) are respectively supplied to terminals 1 and 2, a clear signal is supplied to a terminal 3 and a reference clock having a frequency of 1.2 MHz, for example, is supplied to a terminal 4. The terminals 1 and 2 are respectively electrically connected to one addition input (A2) terminals of adders 5 and 6. A carry output (CO) terminal of the adder 5 is electrically connected to a carry input (CI) terminal of the adder 6. A carry output (CO) terminal of the adder 6 is electrically connected to a carry output terminal 7.
An addition output (S) terminal of the adder 5 is electrically connected to a data (D) input terminal of a D flip-flop 8. A Q output terminal of the D flip-flop 8 is electrically connected to the other addition input (A1) terminal of the adder 5. An addition output (S) terminal of the adder 6 is electrically connected to a data (D) input terminal of a D flip-flop 9. A Q output terminal of the D flip-flop 9 is electrically connected to the other addition input (A1) terminal of the adder 6. Respective clear (CL) input terminals of the D flip-flops 8 and 9 are electrically connected to the terminal 3 and clock (CK) input terminals thereof are electrically connected to the terminal 4.
In the fractional N-type control circuit constructed as described above, a carry signal is supplied to a PLL swallow counter (not shown) as an N+1 signal through the carry output terminal 7. When the 2-bit frequency-divided value data (A, B) are respectively (0, 0), (1,0), (0, 1) and (1, 1), for example, their frequency-divided values are respectively set to 0, 1/4, 2/4 and 3/4. When the frequency-divided value is 1/4, N+1 is supplied or given once every four reference cycles. When the frequency-divided value is 2/4, N+1 is given twice every four reference cycles. When the frequency-divided value is 3/4, N+1 is given three times every four reference cycles.
The operation of the fractional N-type control circuit at the time that the frequency-divided value is 1/4, will now be explained as an example by the following example in which a channel interval is 300 kHz. If a one channel shift occurs when a given channel is defined as N (kHz), then the channel interval becomes N+300 (kHz). If a reference frequency is set to 300 (kHz) at this time, then a PLL can be easily constructed. Since, however, the reference cycle is long, time is required until the PLL is locked. Thus, if the reference frequency is set to 1.2 MHz corresponding to four times the frequency of 300 kHz, for example, then the reference cycle is brought to 1/4. Therefore, the PLL is locked fast as compared with when the reference frequency is 300 (kHz).
As described above, the PLL using 1.2 MHz is locked once per four reference cycles with a frequency large by one reference frequency. Namely, the count of the swallow counter is incremented by 1 once per four reference cycles. In doing so, the PLL is brought to (N+N+N+N+1.2 MHz)/4=N+300 kHz on the average. Thus, the fractional N-type is intended to construct the PLL in which a quick-response frequency is defined as the reference frequency and lock the PLL to a desired frequency by incrementing the count of the swallow counter by 1 n times per m reference cycles.
Since, however, the related art fractional N-type control circuit uses the adders 5 and 6 and has a fedback circuit configuration, the low noise (high C/N) and high-speed lockup characteristics of the fractional N-type PLL frequency synthesizer apparatus are impaired and a relatively high frequency is supplied to the entire circuit for the sake of feedback control. As a result, a problem arises that the current to be used up by the entire PLL unit increases.